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WM8762
24-bit 192kHz Stereo DAC
DESCRIPTION
The WM8762 is a high performance stereo DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8762 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8762 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC in a very small 8-pin SOIC package. The WM8762 supports a 16-24-bit left justified digital audio interface. The WM8762 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in DVD players, including supporting the implementation of 2 channels at 192kHz for high-end DVD-Audio applications.
FEATURES
* * Stereo DAC Audio Performance 98dB SNR (`A' weighted @ 48kHz) -84dB THD Sampling Frequency: 8kHz - 192kHz Audio Data Interface Format 16-24-Bit Left Justified 2.7V - 5.5V Supply Operation 8-pin SOIC Package
* * * *
APPLICATIONS
* * * DVD Players Digital TV Digital Set Top Box
BLOCK DIAGRAM
BCKIN LRCIN DIN SERIAL INTERFACE
MUTE DIGITAL FILTERS MUTE
SIGMA DELTA MODULATOR
RIGHT DAC
VOUTR
SIGMA DELTA MODULATOR
LEFT DAC
VOUTL
W
WM8762
MCLK
VDD
GND
WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com
Preliminary Technical Data, August 2003, Rev 2.0
Copyright 2003 Wolfson Microelectronics plc
WM8762
Preliminary Technical Data
TABLE OF CONTENTS DESCRIPTION ............................................................................................................1 FEATURES..................................................................................................................1 APPLICATIONS ..........................................................................................................1 BLOCK DIAGRAM ......................................................................................................1 PIN CONFIGURATION................................................................................................3 ORDERING INFORMATION .......................................................................................3 PIN DESCRIPTION .....................................................................................................3 ABSOLUTE MAXIMUM RATINGS..............................................................................4 DC ELECTRICAL CHARACTERISTICS .....................................................................5 ELECTRICAL CHARACTERISTICS ...........................................................................5
TERMINOLOGY ................................................................................................................. 6 MASTER CLOCK TIMING .................................................................................................. 7 DIGITAL AUDIO INTERFACE ............................................................................................ 7
DEVICE DESCRIPTION..............................................................................................8
GENERAL INTRODUCTION .............................................................................................. 8 DAC CIRCUIT DESCRIPTION ........................................................................................... 8 CLOCKING SCHEMES ...................................................................................................... 9 DIGITAL AUDIO INTERFACE ............................................................................................ 9 AUDIO DATA SAMPLING RATES...................................................................................... 9 DIGITAL FILTER CHARACTERISTICS.............................................................................10 DAC FILTER RESPONSES...............................................................................................10
TYPICAL PERFORMANCE.......................................................................................11 RECOMMENDED EXTERNAL COMPONENTS .......................................................12
RECOMMENDED EXTERNAL COMPONENTS VALUES .................................................12
RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL) .........................13
PCB LAYOUT RECOMMENDATIONS ..............................................................................13
PACKAGE DRAWING...............................................................................................14 IMPORTANT NOTICE ...............................................................................................15
ADDRESS: ........................................................................................................................15
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Preliminary Technical Data
PIN CONFIGURATION
DIN BCKIN LRCIN MCLK 1 2 3 4 8 VOUTL VDD GND VOUTR
WM8762
7 6 5
ORDERING INFORMATION
DEVICE WM8762ED TEMP. RANGE -25 to +85oC PACKAGE 8-pin SOIC MOISTURE SENSITIVITY LEVEL MSL1
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 NAME DIN BCKIN LRCIN MCLK VOUTR GND VDD VOUTL TYPE Digital input Digital input Digital input Digital input Analogue output Supply Supply Analogue output Serial audio data input Bit clock input Sample rate clock input System master clock input Right channel DAC output Analogue ground supply Positive supply Left channel DAC output DESCRIPTION
Note: Digital input pins have Schmitt trigger input buffers.
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Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020A for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION Supply voltage Voltage range digital inputs Master Clock Frequency Operating temperature range, TA Storage temperature after soldering Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) -25C -65C MIN -0.3V GND -0.3V MAX +7V VDD +0.3V 50MHz +85C +150C +240C +183C
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Preliminary Technical Data
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply range Ground Supply current Supply current Power down current (note 3) SYMBOL VDD GND VDD = 5V VDD = 3.3V VDD=3.3V TEST CONDITIONS MIN 2.7 0 26 20 0.5 TYP MAX 5.5 UNIT V V mA mA mA
ELECTRICAL CHARACTERISTICS
Test Conditions VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH DAC Output (Load = 10k ohms. 50pF) 0dBFS Full scale output voltage SNR (Note 1,2) SNR (Note 1,2) SNR (Note 1,2) SNR (Note 1,2) At DAC outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted, @ fs = 48kHz VDD = 3.3V A-weighted @ fs = 96kHz VDD = 3.3V Non `A' weighted @ fs = 48kHz 1kHz, 0dBFS 1kHz, THD+N @ -60dBFs Load = 10k ohms, 0dBFS Load = 10k ohms, 0dBFS, (VDD = 3.3V) 90 1.2 x VDD/5 98 95 92 95 Vrms dB dB dB dB VIL VIH VOL VOH IOL = 2mA IOH = 2mA 0.9 x VDD 2 0.10 x VDD 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
SNR (Note 1,2)
95
dB
SNR (Note 1,2) THD Dynamic range (Note 2) Analogue Output Levels Output level
92 -84 98
dB dB dB
1.2 0.79
VRMS VRMS
Gain mismatch channel-to-channel Minimum resistance load To midrail or a.c. coupled To midrail or a.c. coupled (VDD = 3.3V) 5V or 3.3V
1 1 1
%FSR kohms kohms
Maximum capacitance load Output d.c. level Power On Reset (POR) POR threshold
100 VDD/2 1.8
pF V V PTD Rev 2.0 August 2003 5
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WM8762
Preliminary Technical Data
Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. Power down occurs 1.5s after MCLK stops.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
3. 4. 5.
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Preliminary Technical Data
MASTER CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 1 Master Clock Timing Requirements Test Conditions o VDD = 5V, GND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK Master clock pulse width high MCLK Master clock pulse width low MCLK Master clock cycle time MCLK Duty cycle Time from MCLK stopping to power down. tMCLKH tMCLKL tMCLKY 8 8 20 40:60 1.5 60:40 12 s ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL AUDIO INTERFACE
tBCH BCKIN tBCY tBCL
LRCIN tDS DIN tDH tLRH tLRSU
Figure 2 Digital Audio Data Timing Test Conditions VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Audio Data Input Timing Information BCKIN cycle time BCKIN pulse width high BCKIN pulse width low LRCIN set-up time to BCKIN rising edge LRCIN hold time from BCKIN rising edge DIN set-up time to BCKIN rising edge DIN hold time from BCKIN rising edge tBCY tBCH tBCL tLRSU tLRH tDS tDH 40 16 16 8 8 8 8 ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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Preliminary Technical Data
DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8762 is a high performance DAC designed for digital consumer audio applications. The range of features make it ideally suited for use in DVD players, AV receivers and other consumer audio equipment. The WM8762 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC design is used, utilising a 128x oversampling rate to optimise signal to noise performance and offer increased clock jitter tolerance. (In `high-rate' operation, the oversampling ratio is 64x for system clocks of 128fs or 192fs) Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled. Sample rates (fs) from less than 8kHz to 192KHz are allowed, provided the appropriate system clock is input. The audio data interface supports a 16-24-bit left justified interface format. A single 2.7-5.5V supply may be used, the output amplitude scaling with absolute supply level. Low supply voltage operation and low current consumption combined with the low pin count small package make the WM8762 attractive for many consumer applications. The device is packaged in a small 8-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8762 DAC is designed to allow playback of 24-bit PCM audio or similar data with high resolution and low noise and distortion. Sample rates up to 192kHz may be used, with much lower sample rates acceptable provided that the ratio of sample rate (LRCIN) to system master clock (MCLK) is maintained at one of the required rates. The two DACs on the WM8762 are implemented using sigma-delta oversampled conversion techniques. These require that the PCM samples are digitally filtered and interpolated to generate a set of samples at a much higher rate than the input rate. This sample stream is then digitally modulated to generate a digital pulse stream that is then converted to analogue signals in a switched capacitor DAC. The advantage of this technique is that the DAC is linearised using noise shaping techniques, allowing the 24-bit resolution to be met using non-critical analogue components. A further advantage is that the high sample rate at the DAC output means that smoothing filters on the output of the DAC need only have fairly crude characteristics in order to remove the characteristic steps, or images, on the output of the DAC. To ensure that generation of tones characteristic to sigma-delta converters is not a problem, dithering is used in the digital modulator and a higher order modulator is used. The multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock jitter, and dramatically reduces out of band noise compared to switched current or single bit techniques used in other implementations. The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers will source load currents of several mA and sink current up to 1.5mA allowing significant loads to be driven. The output source is active and the sink is Class A, i.e. fixed value, so greater loads might be driven if an external `pull-down' resistor is connected at the output. Typically an external low pass filter circuit will be used to remove residual out of band noise characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8762 produces far less out of band noise than single bit traditional sigma delta DACs, and so in many applications this filter may be removed, or replaced with a simple RC pole.
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Preliminary Technical Data
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master clock can be applied directly through the MCLK input pin with no configuration necessary for sample rate selection. Note that on the WM8762, MCLK is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The device can be powered down by stopping MCLK. In this state the power consumption is substantially reduced.
DIGITAL AUDIO INTERFACE
WM8762 supports the left justified audio interface format. The WM8762 supports word lengths of 16-24 bits (MSB first). The word length may be any value up to 24-bits. (If the word length shorter than 24-bits is used, the unused bits will be padded with zeros). In left justified mode, the MSB of DIN is sampled by the WM8762 on the first rising edge of BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 3 Left Justified Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8762 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8762 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The master clock should be synchronised with LRCIN, although the WM8762 is tolerant of phase differences or jitter on this clock. SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz MASTER CLOCK FREQUENCY (MHZ) (MCLK) 128fs 4.096 5.6448 6.114 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9340 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
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WM8762 DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Edge Passband Ripple Stopband Attenuation Table 2 Digital Filter Characteristics SYMBOL TEST CONDITIONS -3dB f < 0.444fs f > 0.555fs -60 MIN TYP 0.487fs
Preliminary Technical Data
MAX 0.05
UNIT dB dB
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 4 DAC Digital Filter Frequency Response -44.1, 48 and 96kHz
Figure 5 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2
0 0 -20
Response (dB)
-0.2
-40
Response (dB)
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 6 DAC Digital Filter Frequency Response - 192kHz
Figure 7 DAC Digital Filter Ripple -192kHz
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Preliminary Technical Data
TYPICAL PERFORMANCE
-65 -70 -75 -80 -85 d B r B -100 -105 -110 -115 -120 -160 -90 -95
-150
-140
-130
-120
-110
-100
-90
-80 dBFS
-70
-60
-50
-40
-30
-20
-10
+0
Figure 8 WM8762 Functionality THD+N VDD = 5V
-70 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 d B r B -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -160 -150 -140 -130 -120 -110 -100 -90 -80 dBFS -70 -60 -50 -40 -30 -20 -10 +0
Figure 9 WM8762 Functionality THD+N VDD = 3V
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WM8762
Preliminary Technical Data
RECOMMENDED EXTERNAL COMPONENTS
VDD + C1 C2
7
VDD
6 AGND
GND
VOUTR
5
C3 + C4 +
WM8762
VOUTL
8
AC-Coupled VOUTR/L to External LPF
3 4 2 1
LRCIN MCLK BCKIN DIN
Audio Serial Data I/F
Notes:
1. C2 should be positioned as close to the WM8762 as possible. 2. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. 3. C3 and C4 not required if using the recommended low pass filter in Figure 9.
Figure 10 External Component Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 C2 C3 and C4 SUGGESTED VALUE 10F 0.1F 10F De-coupling for VDD De-coupling for VDD Output AC coupling caps to remove midrail DC level from outputs DESCRIPTION
Table 3 External Components Description
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Preliminary Technical Data
RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL)
4.7k 4.7k
+VS
_
51 10uF 1.8k 7.5K
+
+
1.0nF 47k 680pF -VS
Figure 11 Recommended Low Pass Filter (Optional) An external low pass filter is recommended (see Figure 20) if the device is driving a wideband amplifier. In some applications, a passive RC filter may be adequate.
PCB LAYOUT RECOMMENDATIONS
Care should be taken in the layout of the PCB that the WM8726 is to be mounted to. The following notes will help in this respect: 1. The VDD supply to the device should be as noise free as possible. This can be accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a 0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on the same layer to minimize track inductance and thus improve device decoupling effectiveness. Separate analogue and digital track routing from each other. The device is split into analogue (pins 5 - 9) and digital (pins 1 - 4 & pins 10 - 14) sections that allow the routing of these signals to be easily separated. By physically separating analogue and digital signals, crosstalk from the PCB can be minimized. Use an unbroken solid GND plane. To achieve best performance from the device, it is advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a 2 layer PCB to be a GND plane. For double sided implementations it is best to route as many signals as possible on the device mounted side of the board, with the opposite side acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions from the PCB and minimizes crosstalk between signals.
2.
3.
An evaluation board is available for the WM8726 that demonstrates the above techniques and the excellent performance achievable from the device. This can be ordered or the User manual downloaded from the Wolfson web site at www.wolfsonmicro.com
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WM8762
Preliminary Technical Data
PACKAGE DRAWING
D: 8 PIN SOIC 3.9mm Wide Body DM009.B
e
8 5
B
E
H
1
4
L
D h x 45o
A
A1 -C-
C
0.10 (0.004)
SEATING PLANE
Symbols A A1 B C D e E h H L REF:
Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 1.27 BSC 3.80 4.00 0.25 0.50 5.80 6.20 0.40 1.27 0o 8o
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.050 BSC 0.1497 0.1574 0.0099 0.0196 0.2284 0.2440 0.0160 0.0500 0o 8o
JEDEC.95, MS-012
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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Preliminary Technical Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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